This invention relates, generally, to the fabrication of semiconductor devices and, more particularly, to the fabrication of non-volatile memory devices such as EEPROM devices, and the like.
Non-volatile memory devices are currently in widespread use in to electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state.
Since the operation of an EEPROM device depends upon the presence or absence of charge on the floating-gate electrode, memory manufacturers typically take steps to ensure that all memory cells are erased prior to shipment of memory devices to customer. Typically the data-erase operation involves applying appropriate erase voltages to the memory array in order remove electrical charge from the floating-gate electrodes in the array. It is important that no electrical charge remain on any floating-gate electrode in a memory array prior to shipment. Extraneous charge in the memory array can result in programming errors and other operational anomalies.
Advances in EEPROM device technology have led to the use of certain dielectric materials for the fabrication of floating-gate electrodes. For example, advanced EEPROM devices can be fabricated with silicon nitride floating-gate electrodes. Silicon nitride is among a group of dielectric materials that possess the capability to store electrical charge in isolated regions within the dielectric material. The ability of silicon nitride to store electrical charge in isolated regions has led to its use in advance EEPROM technology, such as two-bit non-volatile memory devices.
Although the ability of materials, such as silicon nitride and the like, to store electrical charge in isolated regions has enabled the fabrication of advanced EEPROM devices. Memory cells incorporating silicon nitride as a charge storage layer must be carefully fabricated. The storage and removal of electrical charge from isolated regions of a single layer of silicon nitride in an EEPROM memory cell requires that adequate steps to taken to ensure that extraneous electrical charge does not inadvertently remain on floating-gate electrodes prior to device shipment. According, advances in non-volatile fabrication technology are necessary to ensure proper programming and operation of non-volatile memory devices incorporating floating-gate electrodes fabricated with dielectric materials.
The present invention is for a process for fabricating a non-volatile memory device in which extraneous electrical charge is removed from charge-storage layers during fabrication of the non-volatile memory device. By taking steps to remove electrical charge from charge-storage wires during device fabrication, extraneous electrical charge induced during fabrication can be efficiently removed. For example, extraneous electrical charge can be generated by conventional processing operations, such as chemical-vapor-deposition (CVD), plasma etching and the like. The process of the present invention efficiently removes process-induced electrical charge by exposing the charge-storage layer to infrared radiation during device fabrication. The inventive process incorporates infrared radiation exposure of the charge-storage layer at a point in the process prior to the formation of overlying layers, such as control-gate electrodes, interlevel dielectric layers, metal interconnect layers, and the like. By exposing the charge-storage layer at an intermediate point in the fabrication process, a high efficiency charge removal methodology is realized.
In one form, a process is provided in which a charge-storage layer is formed to overlie a semiconductor substrate. The charge-storage layer has exposed surface regions which are bombarded by infrared radiation to remove electrical charge from the charge-storage layer.